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SX1210
ADVANCED COMMUNICATIONS & SENSING
4. Operating Modes
This section summarizes the settings for each operating mode of the SX1210, and explains the functionality
available and the timing requirements for switching between modes.
4.1. Modes of Operation
Table 10: Operating Modes
Mode
Sleep
Standby
FS
Receive
MCParam_Chip_mode
000
001
010
011
Active blocks
SPI, POR
SPI, POR, Top regulator, digital regulator, XO, CLKOUT (if activated through
OSCParam_Clkout)
Same + VCO regulator, all PLL and LO generation blocks
Same as FS mode + LNA, first mixer, IF amplifier, second mixer set, channel
filters, baseband amplifiers and limiters, RSSI, OOK or FSK demodulator,
BitSync and all digital features if enabled
4.2. Digital Pin Configuration vs. Chip Mode
Table 11 describes the state of the digital IOs in each of the above described modes of operation, regardless of the
data operating mode.
Table 11: Pin Configuration vs. Chip Mode
Chip
………. Mode
Sleep
mode
Standby
mode
FS mode
Receive
mode
Comment
Pin
NSS_CONFIG
NSS_DATA
MISO
MOSI
SCK
IRQ_0
IRQ_1
DATA (3)
CLKOUT
PLL_LOCK
Input
Input
Input
Input
Input
High-Z
High-Z
High-Z
High-Z
High-Z
Input
Input
Input
Input
Input
Output (1)
Output (1)
High-Z
Output
Output (4)
Input
Input
Input
Input
Input
Output (1)
Output (1)
High-Z
Output
Output (4)
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
(4)
NSS_CONFIG has the priority over
NSS_DATA
Output only if NSS_CONFIG or
NSSDATA=’0’
Notes:
(1): High-Z if Continuous mode is activated, else Output
(2): Valid logic states must be applied to inputs at all times to avoid unwanted leakage currents
(3): Tie to Vss (or Vdd) when not in active receive mode.
(4): Output if PLL_lock_en = 1, else High-Z
Rev 2– Sept 8 , 2008
th
Page 27 of 73
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